/*
 * Copyright 2015 Vishnu Patekar
 *
 * Vishnu Patekar <vishnupatekar0510@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 * $FreeBSD: head/sys/boot/fdt/dts/arm/sun8i-a83t.dtsi 299748 2016-05-14 18:47:36Z jmcneill $
 */

#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};

		cpu@100 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu@101 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu@102 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu@103 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* TODO: PRCM block has a mux for this. */
		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		/*
		 * This is called "internal OSC" in some places.
		 * It is an internal RC-based oscillator.
		 * TODO: Its controls are in the PRCM block.
		 */
		osc16M: osc16M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <16000000>;
			clock-output-names = "osc16M";
		};

		osc16Md512: osc16Md512_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <512>;
			clock-mult = <1>;
			clocks = <&osc16M>;
			clock-output-names = "osc16M-d512";
		};

		pll6: clk@01c20028 {
			#clock-cells = <0>;
			compatible = "allwinner,sun9i-a80-pll4-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6";
		};

		pll6d2: pll6d2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <2>;
			clock-mult = <1>;
			clocks = <&pll6>;
			clock-output-names = "pll6d2";
		};

		ahb1: clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a83t-ahb1-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
			clock-output-names = "ahb1";
		};

		apb1: apb1_clk@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-a83t-apb1-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		apb2: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
			clock-output-names = "apb2";
		};

		ahb2: clk@01c2005c {
			#clock-cells = <0>;
			compatible = "allwinner,sun8i-h3-ahb2-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&ahb1>, <&pll6d2>;
			clock-output-names = "ahb2";
		};

		bus_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-a83t-bus-gates-clk";
			reg = <0x01c20060 0x10>;
			clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
			clock-names = "ahb1", "ahb2", "apb1", "apb2";
			clock-indices = <1>, <5>, <6>,
					<8>, <9>, <10>,
					<13>, <14>, <17>,
					<19>, <20>,
					<21>, <24>,
					<26>, <27>,
					<29>, <32>,
					<36>, <37>,
					<40>, <43>,
					<44>, <52>, <53>,
					<54>, <65>,
					<69>, <76>, <77>,
					<78>, <79>, <96>,
					<97>, <98>,
					<112>, <113>,
					<114>, <115>,
					<116>;
			clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
					     "bus_mmc0", "bus_mmc1", "bus_mmc2",
					     "bus_nand", "bus_sdram", "bus_emac",
					     "bus_hstimer", "bus_spi0",
					     "bus_spi1", "bus_usb_otg",
					     "bus_ehci0", "bus_ehci1",
					     "bus_ohci0", "bus_ve",
					     "bus_lcd0", "bus_lcd1",
					     "bus_csi", "bus_hdmi",
					     "bus_de", "bus_gpu", "bus_msgbox",
					     "bus_spinlock", "bus_spdif",
					     "bus_pio", "bus_i2s0", "bus_i2s1",
					     "bus_i2s2", "bus_tdm", "bus_i2c0",
					     "bus_i2c1", "bus_i2c2",
					     "bus_uart0", "bus_uart1",
					     "bus_uart2", "bus_uart3",
					     "bus_uart4";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
		};

		cpus_clk: clk@01f01400 {
			compatible = "allwinner,sun9i-a80-cpus-clk";
			reg = <0x01f01400 0x4>;
			#clock-cells = <0>;
			clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
			clock-output-names = "cpus";
		};

		ahb0: ahb0_clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&cpus_clk>;
			clock-output-names = "ahb0";
		};

		apb0: clk@01f0140c {
			compatible = "allwinner,sun8i-a23-apb0-clk";
			reg = <0x01f0140c 0x4>;
			#clock-cells = <0>;
			clocks = <&ahb0>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01f01428 {
			compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
			reg = <0x01f01428 0x4>;
			#clock-cells = <1>;
			clocks = <&apb0>;
			clock-indices = <0>, <1>,
					<2>, <3>,
					<4>, <6>, <7>;
			clock-output-names = "apb0_pio", "apb0_ir",
					"apb0_timer", "apb0_rsb",
					"apb0_uart", "apb0_i2c0", "apb0_twd";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&bus_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb_reset 8>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&bus_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb_reset 9>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun5i-a13-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&bus_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ahb_reset 10>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun8i-a83t-pinctrl";
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x01c20800 0x400>;
			clocks = <&bus_gates 69>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0", "PF1", "PF2",
						 "PF3", "PF4", "PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
				allwinner,pins = "PF6";
				allwinner,function = "gpio_in";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PB9", "PB10";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		ahb_reset: reset@01c202c0 {
			reg = <0x01c202c0 0xc>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			#reset-cells = <1>;
		};

		apb1_reset: reset@01c202d0 {
			reg = <0x01c202d0 0x4>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			#reset-cells = <1>;
		};

		apb2_reset: reset@01c202d8 {
			reg = <0x01c202d8 0x4>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			#reset-cells = <1>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&bus_gates 112>;
			resets = <&apb2_reset 16>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb0_reset: reset@01f014b0 {
			reg = <0x01f014b0 0x4>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			#reset-cells = <1>;
		};

		r_pio: pinctrl@01f02c00 {
			compatible = "allwinner,sun8i-a83t-r-pinctrl";
			reg = <0x01f02c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 0>;
			resets = <&apb0_reset 0>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			r_rsb_pins: r_rsb {
				allwinner,pins = "PL0", "PL1";
				allwinner,function = "s_rsb";
				allwinner,drive = <SUN4I_PINCTRL_20_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};
		};

		r_rsb: i2c@01f03400 {
			compatible = "allwinner,sun8i-a23-rsb";
			reg = <0x01f03400 0x400>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 3>;
			clock-frequency = <3000000>;
			resets = <&apb0_reset 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&r_rsb_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};